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1/22 MSC1215-XX ? semiconductor general description the MSC1215-XX is a 1/2-duty vacuum fluorescent display tube driver implemented in bi- cmos technology. this lsi consists of a 37-bit shift register, 34 latches, an analog dimming circuit, (a pwm conversion circuit), a 3 4 keyscan circuit, a 6ch-6-bit a/d converter and 17 segment drivers, and 2-grid pre-drivers. the MSC1215-XX has capabilities of displaying audio system frequencies and various informa- tions on a vfd tube for the automobile application and also interfacing with keyboard inputs and on an analog volume input. for automobile audio systems, the front panel functions (such as a frequency display, keyboard input and analog voltage input from a volume) can be accomplished by this ic. the analog dimming/pwm conversion modes can be selected automatically for the brightness control, so this ic is applicable to any type of automobile without any change of the specifica- tions. the interface with a mcu can be done only with 3 wires (cs, data i/o and clock signals). also, data i/o and clock signal lines can be shared with other peripherals because of chip select function by cs signal. features ? power supply voltage : v dd =8 to 18 v ? operating temperature range : ta=C40 to +85 c) ? 17-segment driver outputs (i oh =C5ma at v oh =v dd C0.8 v) ? built-in analog dimming circuit (6-bit resolution, user-programmable) ? built-in pwm conversion circuit (lamp pwm signal to vacuum fluorescent display pwm signal) ? built-in automatic-selection circuit for analog dimming/pwm conversion function ? built-in 6ch 6-bit a/d converter ? built-in 3 4 keyscan circuit ? built-in oscillation circuit (external r and c, f osc =3.3 mhz) ? built-in power-on-reset circuit ? package: 42-pin plastic dip (dip 42-p-600-2.54) (product name: msm1215-xxrs) xx indicates the code number. ? semiconductor MSC1215-XX 17 2 duplex driver with dimming, keyscan and a/d converter function e2c0022-27-y3 this version: nov. 1997 previous version: jul. 1996
2/22 MSC1215-XX ? semiconductor block diagram grid1 grid2 vk vd osc1 + + - v dd gnd cs data i/o osc0 clock sw2 sw1 pwmout 5v seg1 seg17 34 ? 17 segment control 17 segment vf tube driver p. o. r regulator bit 34-18 (grid2) bit 17-1 (grid1) 34-bit latch l d bit34 bit1 test mode select 3-bit latch test1-8 sw1 (vf data) sw2 (keyscan) sw3 (a/d) 3-bit s/r 34-bit shift register to pwm out timing r timing generator grid pre-driver osc mux latch pwm logarithm counter select d/a decoder de-glitch pwm detector look up table 6-bit dig. comp. sw3 si set s s pe out lll 444 444 4-bit latch timing generator detector read enable "h"at sw2 on row col channel select timing generator pe o 36-bit s/r 6ch 6-bit a/d & logic "h" at sw3 on read eable ch1 ch2 ch3 ch4 ch5 ch6 v ref v ref 12-bit presetable s/r with 100k w pull-up resistor - 321 321 4
3/22 MSC1215-XX ? semiconductor input and output configuration ? schematic diagrams of logic portion input circuit 1 ? schematic diagrams of logic portion input circuit 2 ? schematic diagrams of logic portion input/ output circuit ? schematic diagrams of logic portion output circuit ? schematic diagrams of driver output circuit gnd v dd gnd input (5v reg.) gnd (5v reg.) v dd gnd coln gnd (5v reg.) v dd gnd datai/o gnd (5v reg.) gnd gnd (5v reg.) gnd output (5v reg.) gnd v dd gnd output v dd
4/22 MSC1215-XX ? semiconductor pin configuration (top view) col4 1 col3 42 grid1 2 col2 41 grid2 3 col1 40 seg 1 4 vd 39 seg 2 5 v ref 38 seg 3 6 ch6 37 seg 4 7 ch5 36 seg 5 8 ch4 35 seg 9 9 ch3 34 seg10 10 ch2 33 seg11 11 ch1 32 v dd 12 gnd 31 seg12 13 osc0 30 seg13 14 osc1 29 seg14 15 vk 28 seg15 16 data i/o 27 seg16 17 cs 26 seg17 18 clock 25 seg 6 19 row 1 24 seg 7 20 row 2 23 seg 8 21 row 3 22 42-pin plastic dip
5/22 MSC1215-XX ? semiconductor absolute maximum ratings recommended operating condition parameter supply voltage high level input voltage (2) symbol typ. unit v dd t op v ih2 8 v max. 18 5.5 85 low level input voltage clock frequency osc frequency condition all inputs C40 3.8 3.33 250 0.8 c v v v il f osc v ih1 high level input voltage (1) operating temperature min. f c v dd 3.8 0 vk all inputs except vk r=4.7 k w , c=10 pf v khz mhz frame frequency 200 f fr hz parameter supply voltage input voltage (1) symbol condition rating unit v dd v in1 all inputs except vk C0.3 to +20 v v c storage temperature C0.3 to +v dd ta=85c t stg C55 to +150 input voltage (2) power dissipation v in2 p d vk C0.3 to +6 400 v mw
6/22 MSC1215-XX ? semiconductor electrical characteristics dc characteristics parameter "h" input voltage symbol min. unit v ih v il 3.8 v max. 0.8 "l" input voltage condition all inputs except vd C5 v dd -0.8 4 4.5 1 0.3 2 C10 20 5 5 C5 v v ma m a f osc =3.3 mhz, no load i dd "h" input current (1) "h" input current (2) "l" input current (1) "l" input current (2) "h" output voltage (1) "l" output voltage (1) "l" output voltage (2) all inputs except col1-4 v in =4.4 v data i/o, v dd =9.5 v i oh2 =C200 m a output open seg,grid, v dd =9.5 v i ol1 =500 m a i ol1 =200 m a i ol1 =2 m a current consumption i ih1 i ih2 i il1 i il2 v oh1 v ol1 v ol2 C70 C160 C5 0.8 v m a m a m a v v v (ta=C40 to +85c, v dd =8 to 18v) "h" output voltage (2) v oh2 all inputs except vd col1-4, v in =3.8 v all inputs except col1-4 v in =0 v col1-4, v in =0 v seg, grid i oh1 =C5 ma, v dd =9.5 v data i/o, row1-3 v dd =9.5 v, i ol2 =200 m a v v
7/22 MSC1215-XX ? semiconductor switching characteristics parameter clock frequency symbol min. unit f c t dh 200 8 khz max. 250 data hold time condition except reset mode 32 1.3 1 8 5 1 m s clock pulse width data set-up time cs off time cs pulse width c l =100 pf c l =100 pf t=20% to 80% or 80% to 20% of v dd t cw t ds t csw t csl t css t csh t pd t ods t r t pcs 2 2 300 m s m s m s m s cs set-up time cs-clock time cs hold time clock-cs time data output delay clcok-data out time seg & grid outputs delay time from cs slew rate (all drivers) power on timing m s m s ns m s m s m s (ta=C40 to +85c, v dd =8 to 18 v) oscillation frequency f osc mhz 4.5 2 cs off time cs pulse width t rcsw t rcsl except reset mode reset mode reset mode 4 4 m s m s
8/22 MSC1215-XX ? semiconductor analog dimming characteristics a/d converter characteristics keyscan characteristics pwm conversion characteristics parameter d/a ouput voltage error typ. unit % max. 3 6 condition % reference voltage accuracy min. (ta=C40 to +85c, v dd =8 to 18v) *1 *1 reference voltage is 6.6 v typical. *2 when six loads of 10 k w are connected in parallel. parameter keyscan cycle time typ. unit m s max. 512 128 condition m s keyscan pulse width min. 312 78 f osc =3.3mhz 220 55 (ta=C40 to +85c, v dd =8 to 18 v) f osc =3.3mhz parameter pwm input frequency typ. unit hz max. 132 800 condition t r =10% ? 90%, t f =90% ? 10% rise/fall time min. 122 300 vd pin 112 100 (ta=C40 to +85c, v dd =8 to 18 v) pwm pulse width input duty cycle "h" input threshold voltage vd pin 125 1.65 0.20v dd 0.28v dd 98.3 0.30v dd % m s "l" input threshold voltage hysteresis width vd pin vd pin t=50% ? 50% 0.26v dd 0.02v dd 0.22v dd 0.06v dd 0.10v dd 0.24v dd v v m s v parameter a/d conversion accuracy typ. unit lsb max. 1 5.5 condition *2 v reference voltage (v ref ) min. 5 f osc =3.3mhz 4.5 (ta=C40 to +85c, v dd =8 to 18 v) output current input voltage range conversion time/channel gnd 384 543 4 v ref 896 ma v m s
9/22 MSC1215-XX ? semiconductor timing diagram t ds data i/o (input) t csw t csl t css f c cs clock t cw t cw t csh t ds valid valid t dh t dh 3.8 v 0.8 v 3.8 v 0.8 v 3.8 v 0.8 v figure 1. data input timing cs data i/o (output) clock 3.8 v 0.8 v 3.8 v 0.8 v 3.8 v 0.8 v t css t csh t pd t pd figure 2. data outpout timing
10/22 MSC1215-XX ? semiconductor v dd cs 3.8 v 0.8 v 8 v t pcs t rcsw t rcsl figure 3. power-on-reset timing cs 3.8 v 0.8 v t r seg1-17 80% 20% grid1, 2 t csw t ods t ods t r figure 4. seg and grid output timing figure 5. seg- grid output timing (daylight mode) note: 1. timing shown for analog dimming with a duty cycle of 2032/2048 at vk="l". 2. 1-bit time=t osc (=4/f osc )=1.2 m s typical. grid1 16-bit times min 6-bit times 2032-bit times 2038-bit times 10-bit times 1 frame cycle f fr 4096-bit times grid2 seg1-17
11/22 MSC1215-XX ? semiconductor figure 6. seg- grid output timing (dark mode) note: 1. timing shown for analog dimming with a duty cycle of 208/2048 at vk="h". 2. 1-bit time=t osc (=4/f osc )=1.2 m s typical. 90% t r t pw 50% 10% vd (pwm input) t t f figure 7. pwm waveform row1 row2 row3 keyscan cycle time keyscan pulse width figure 8. keyscan timing note: 1. key scanning from row1 to row3 is started when any key is pushed down or released. scanning will stop when cs turns to "l" from "h", after 2 times of cs pulses and the transfer of display data. grid1 grid2 seg1-17 4096-bit times 1 frame cycle f fr 2048-bit times 208-bit times max.
12/22 MSC1215-XX ? semiconductor cs keyscan stop keyscan display data output push figure 9. keyscan stop timing functional description pin functional description ?v dd power supply input pin connected to a 12v power supply ? gnd ground pin this pin is 0v level. ? clock serial clock input pin ?cs chip select input pin when "h" is input to this pin, interfacing with a mcu is available through the clock and the data pins. therefore, 2 signal lines of the clock and the data can be shared with other peripherals. ? data i/o (input-output) serial data input-output pin this pin inputs display data and outputs keyscan and a/d conversion data. ?vk daylight/dark mode selection input pin when "h" is input, the dark mode is selected and an output duty cycle is determined by analog or pwm data input into the vd pin. when "l" is input, the daylight mode is selected and the output duty cycle becomes about 100%. ?vd analog/pwm dimming data input pin analog/pwm dimming mode selection will be done by an internal detection circuit automati- cally. ?v ref reference voltage output pin for the a/d converter
13/22 MSC1215-XX ? semiconductor ? ch1-6 analog voltage input pin for the a/d converter ? col1-4 key matrix input pins these pins are active "low" and pulled up to "h" through built-in resistors except when "l" is input by a pushed down key. ? row1-3 key matrix scanning output normally row1-3 output "l", by detecting the key switch to be pushed down or released, a key scan starts, sending cs pulses two times and vf data, after above turning the cs pin to "l" from "h". after scan stops, all the row outputs turn to "l". ? osc0, 1 rc oscillation input pins a resistor and a capacitor are connected to these pins. (see figure below) osc1 osc0 r c ? seg1-17 segment output pins ? grid1 , 2 grid output pins output an inverted signal of a grid signal. these pins are connected to inputs of external drivers (such as a pnp transistor).
14/22 MSC1215-XX ? semiconductor functional flowchart power-on (power-on reset) display data input mode dispaly data input test data input input total (34 bits) (3 bits) (37 bits) cs="l" cs="h" 2cs pulses a/d data output mode a/d data output (36 bit) keyscan data output (12 bits) cs="l" cs="h" cs="l" cs="h" keyscan data output mode *1 *2 note: 1. when power supply turns on, the internal circuits are initialized as follows by the built-in power-on reset circuit. ? display data input mode is selected ? all segment outputs are in off state ("l") ? all internal registers and latches are set to "0" level 2. the status of the internal circuit after serial 2 cs pulses were applied, are as follows. ? display data input mode is selected ? the other status are the same as before the serial 2cs pulses were applied.
15/22 MSC1215-XX ? semiconductor display data input data input is available only when "h" is applied to the "cs" pin. input data is shifted into shift registers through the "data i/o" pin at the rising edge of the clock. the data is automatically loaded to latches at the falling edge of "cs" signal. [data format] 37 bit first in *1 data 34 36 33 35 32 6 3 5 2 4 1 3 t3 2 t2 1 t1 display data test data note: three bits (t1 to t3) for the test data are used for shipping inspection. for the normal operation mode, all these bits should be set to "0" level. keyscan data output data output is available only when "h" is applied to the "cs" pin. when keyscan data output mode is selected, "data i/o" pin is changed to an output mode. then, 12 bits of keyscan data come out from "data i/o" pin synchronizing with the rising edge of the clock. this output mode is changed to a/d data output mode at the falling edge of the cs input signal. to select directly the display input mode from this output mode, serial 2cs pulses should be input to the cs pin. [data format] 12 bit first out *2 data s34 11 s33 10 s32 6 s21 5 s14 4 s13 3 s12 2 s11 1 9 s31 8 s24 7 s23 s22 note: symbols of the keyscan data are as follows. s rc col number (col1-4) row number ( row1-3 ) a/d data output a/d data output is available only when "h" is input to the cs pin. when the a/d data output mode is selected, data i/o pin is changed to an output mode. then 36 bits of a/d data come out from data i/o pin synchronizing with the rising edge of the shift clock. this output mode is changed to the display input mode at the falling edge of the cs input signal. [data format] 36-31 bit first out data msb-lsb ch6 30-25 msb-lsb ch5 24-19 msb-lsb ch4 18-13 msb-lsb ch3 12-7 msb-lsb ch2 6-1 msb-lsb ch1
16/22 MSC1215-XX ? semiconductor keyscan to keep a scanning noise to a minimum, a scanning of the key switch starts only when a key is pushed down or released. the scanning stops when cs input turns to "l" from "h" after sending cs pulses two times and display data. [key matrix of col input and row output] row1 row2 row3 col1 col2 col3 col4 = s11 s21 s31 s12 s22 s32 s13 s23 s33 s14 s24 s34 a/d conversion the ic has a built-in 6-ch 6-bit a/d converter. as shown in the circuit below, the v ref output pin is connected to a variable resistor forming a voltage divider and the divided analog voltage is used to input into the ch1 to ch6 pins. [circuit example] v ref ch1 variable resistor pwm dimming lamp pwm signal is input to the vd pin and converted to vf display pwm signal by the pwm conversion circuit. the conversion table is mark-programmable. note: the duty cycle of the lamp pwm signal is measured with a reference point of the threshold voltage of the vd input pin. the threshold voltage changes due to process parameter deviation. therefore, the pwm conversion error increases as the rise/fall time of the lamp pwm increases.
17/22 MSC1215-XX ? semiconductor analog dimming the pwm duty cycle is controlled by analog voltage which is the output of the brightness control volume on a dashboard. the dimming curve is mask-programmable with the following limitations; 1. maximum duty cycle is 12.5%. 12.5% max 12.5% 100% (duty) 512khz duty cycle step 2. number of pulse stops is max. 52. 3. input voltage to "vd" the input voltage to "vd" needs to use a voltage divider as shown below. vd-in vd 2r r note: the maximum voltage to the vd is 5v. 4. maximum threshold voltage the maximum threshold voltage is 5.0v. 5. minimum & maximum vdim input voltage the minimum threshold voltage step is 20mv. only for the first step, the threshold voltage can be any value between 20mv and 3v. min 20mv max 3v 3 2 1 0
18/22 MSC1215-XX ? semiconductor pwm conversion table step no. lamp pwm duty cycle 12.50% 100.00% 98.75% 97.50% 96.25% 95.00% 93.75% 92.50% 91.25% 90.00% 88.75% 87.50% 86.25% 85.00% 83.75% 82.50% 81.25% 80.00% 78.75% 77.50% 76.25% 75.00% 73.75% 72.50% 71.25% 70.00% 68.75% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 step no. vfd pwm duty cycle lamp pwm duty cycle vfd pwm duty cycle 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 67.50% 66.25% 65.00% 63.75% 62.50% 61.25% 60.00% 58.75% 57.50% 56.25% 55.00% 53.75% 52.50% 51.25% 50.00% 48.75% 47.50% 46.25% 45.00% 43.75% 42.50% 41.25% 40.00% 38.75% 37.50% 36.25% 35.00% 33.75% 32.50% 31.25% 30.00% 28.75% 27.50% 26.25% 25.00% 23.75% 22.50% 21.25% 20.00%
19/22 MSC1215-XX ? semiconductor dimming voltage-pulse width correspondence table vdi threshold dimming voltage vs. pwm duty cycle (typical value) 12.5% pwm maximum table pulse step number pulse step number pwm duty cycle pulse count % % pulse count pwm duty cycle threshold voltage threshold voltage 12.5 11.7 10.9 10.2 9.38 8.98 8.59 8.20 7.81 7.42 7.03 6.64 6.25 5.86 5.47 5.08 4.69 4.49 4.30 4.10 3.91 3.71 3.52 3.32 3.13 2.93 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 256/2048 240/2048 224/2048 208/2048 192/2048 184/2048 176/2048 168/2048 160/2048 152/2048 144/2048 136/2048 128/2048 120/2048 112/2048 104/2048 96/2048 92/2048 88/2048 84/2048 80/2048 76/2048 72/2048 68/2048 64/2048 60/2048 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 56/2048 52/2048 48/2048 46/2048 44/2048 42/2048 40/2048 38/2048 36/2048 34/2048 32/2048 30/2048 28/2048 26/2048 24/2048 23/2048 22/2048 21/2048 20/2048 19/2048 18/2048 17/2048 16/2048 15/2048 14/2048 13/2048 2.73 2.54 2.34 2.25 2.15 2.05 1.95 1.86 1.76 1.66 1.56 1.46 1.37 1.27 1.17 1.12 1.07 1.03 0.98 0.93 0.88 0.83 0.78 0.73 0.68 0.63 0.000 (@v dd =2.8 v)
20/22 MSC1215-XX ? semiconductor application circuits dimming mode small lamp switch seg1 seg17 12 v dd grid1 grid2 osc1 gnd datai/o clock cs v ref ch1 ch6 vk vd MSC1215-XX 1/2 duty vf display tube 123 3 4 12 v row col osc0 12 v dashboard lamp lamp pwm signal 12 v 12 v microcontroller
21/22 MSC1215-XX ? semiconductor analog dimming mode small lamp switch seg1 seg17 12 v dd grid1 grid2 osc1 gnd datai/o clock cs v ref ch1 ch6 vk vd MSC1215-XX 1/2 duty vf display tube 123 3 4 12 v row col osc0 12 v dashboard lamp brightness control resistor 12 v 12 v microcontroller
22/22 MSC1215-XX ? semiconductor (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip42-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.20 typ.

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